<< Submission deadline: April 8th, 2015 (Firm deadline) >>
Many-core embedded systems (MES) are moving towards the integration of hundreds
of cores on a single chip and hold the promise of increasing performance through parallelism.
As the number of cores integrated into a chip increases, the on-chip communication becomes a power and performance bottleneck in future MESs. On-chip network has been
proposed as the most viable solution to meet the performance and design productivity requirements of the complex on-chip communication infrastructure. NoCs provide
an infrastructure for better modularity, scalability, fault-tolerance, and higher bandwidth compared to traditional infrastructures. On the other hand, developing applications
using the full power of MES requires software developers to transition from writing serial programs to writing parallel programs. On top of that,
contemporary Operating Systems (OS) have been designed to run on a small number of reliable cores and are not able to scale up to hundreds of cores. Therefore, designing
scalable and fault-tolerant OSs will be a tremendous challenge in future MESs.
As neuromorphic and mixed-signal architectures are emerging as an alternative solution beyond the conventional digital von Neumann machines
for complex applications, we would like to highlight such emerging architectures in this workshop.
In addition, we would like to emphasize on energy efficient (real-time) data processing in the realm of Big data and IoT applications through MESs.
The goal of this workshop is to bring together the researchers from academia and the experts from industry to present and discuss innovative ideas and solutions in the design, modeling, prototyping, programming, and implementation of MES. Topics of
interest include, but are not limited to:
- Neuromorphic Architectures
- Applications mapping
- (Embedded) OS
- Real-time and mixed-criticality
- 3D Stacked Architectures
- Reliability issues
- Physical design
- Synthesis, verification, debug & test
- Performance and power issues
- Reconfigurability aspects
- FPGA implementation
- Prallel programming models and scalable software
- Compiler technologies
- Many-core as accelerators
- Heterogeneity challenges
- Data-centers and supercomputers
- Dynamic power management and energy
Submissions from EU projects in progress as well as seminal work in the field are also encouraged. Submissions should not exceed 8 pages, including tables and figures, and must
be formatted in accordance to the ACM two column style. Submission of a paper should be regarded as an undertaking whereby, should the paper be accepted, at least one of the authors
will register for the conference and present the work.
The proceeding will be published in the ACM Digital Library and
Selected papers will be considered to appear in a special issue of the Elsevier's Microprocessors and Microsystems.